The processor core is an optimized five-stage pipeline with a 64-bit data path, based on MIPS architecture. The core incorporates a memory management unit (MMU). The MMU's 48-double entry translation lookaside buffer (TLB) with its fourway set-associative 32-KByte instruction and data caches allows the core to meet Windows CE MMU requirements. A hardware multiply accumulator (MAC) and single/double-precision floating-point unit (FPU) are also integrated with the core. The instruction set supports MIPS I, II, and III instructions, plus MIPS IV prefetch, multiply/add and debug instructions.
External to the microprocessor core, the chip's integrated SDRAM memory controller can handle four channels of registered/non-registered DIMM SDRAM (100-MHz max.) with ECC, in configurations up to two GBytes. An external bus controller supports eight channels of ROM, Flash and memory-mapped I/O devices. A PCI bus controller supports either four 33-MHz or two 66-MHz bus masters. It fully complies with revision 2.2 of the PCI Local Bus Specification with PCI booting. A DMA controller supports four independent channels plus one channel for specialized PCI, interrupt controllers capable of monitoring 18 different sources, two UART channels, three 32-bit timer/counter channels, and 16-bit bi-directional parallel-IO ports.
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